A memory, such as a static random access memory (SRAM), typically comprises a plurality of memory cells each of which stores a bit of information. A memory cell 100 that is typically used in an SRAM is depicted in FIG. 1. The memory cell 100 is a six transistor cell and includes a first inverter 102 and a second inverter 104. The first inverter 102 includes MOSFETs 106 and 108, and the second inverter 104 includes MOSFETs 110 and 112.
The source terminals of the MOSFETs 106 and 110 are connected to a source VSS, and the source terminals of the MOSFETs 108 and 112 are connected to a supply VDD. The first and second inverters 102 and 104 are cross coupled. Accordingly, the gate terminals of the MOSFETs 106 and 108 are connected to the drain terminals of the MOSFETs 110 and 112, and the gate terminals of the MOSFETs 110 and 112 are connected to the drain terminals of the MOSFETs 106 and 108.
A first transmission gate 114, also known as a pass gate, includes a MOSFET having a first source/drain terminal connected to the drain terminals of the MOSFETs 106 108, a second source/drain terminal connected to a bit line BL, and a gate terminal connected to a non-inverted word line WL. Also, a second transmission gate 116, or pass gate, includes a MOSFET having a first source/drain terminal connected to the drain terminals of the MOSFETs 110 and 112, a second source/drain terminal connected to an inverted bit line NBL, and a gate terminal connected to the non-inverted word line WL.
Each memory cell within the SRAM may be vulnerable to high-energy particles from a radiation harsh environment. These high-energy particles may cause a Single Upset Event (SEU) in a memory cell, which is a change in the stored state of the memory cell. The SEU may occur when a high-energy particle deposits a charge on a given node within the memory cell. The charge threshold at which the SEU may occur is called the critical charge of the memory cell.
Heavy ions are typically considered the dominating cause for SEUs. Heavy ions may be capable of depositing relatively large amounts of charge on a memory cell node. The large deposited charge may force the memory cell node from its original state to an opposite state for some period of time. If the memory cell node is held in the opposite state for a period longer than the delay around the memory cell feedback loop, the memory cell will switch states and the data will be lost.
In addition, protons and neutrons may also cause SEUs. Protons and neutrons typically do not deposit enough charge on a memory cell node to cause an SEU, but protons or neutrons may interact with a Si nuclei of the SRAM. The interaction between the protons or neutrons and the Si nuclei may create secondary high-energy particles, which are also known as recoiling heavy ions. The recoiling heavy ions may be able to travel through a Si lattice and reach the memory cell node. If the recoiling heavy ion does reach the memory cell node, the recoiling heavy ion may cause a SEU under certain conditions.
Many design techniques for reducing the sensitivity of SRAM cells to SEUs caused by high energy particles have been proposed previously. One common design technique to make an SRAM cell more SEU hardened is to add an active delay element between the cross coupled inverters of the SRAM cell. A memory cell 200 with a cross-connected active delay element is depicted in FIG. 2. The memory cell 200 is substantially the same as the memory cell 100 in FIG. 1, except that first and second inverters 202 and 204 are cross-connected through an active delay element 218. Accordingly, the gate terminals of MOSFETs 206 and 208 are connected directly to the drain terminals of the MOSFETs 210 and 212, and the gate terminals of the MOSFETs 210 and 212 are connected to the drain terminals of the MOSFETs 206 and 208 through the active delay element 218.
The active delay element 218 may include a switch transistor. The switch transistor may take various forms. For example, the switch transistor may be a single enhancement-mode NMOSFET, or the switch transistor may be a single enhancement-mode PMOSFET. The gate of the switch transistor may be connected to a word line, and the switch transistor may be turned on during a write operation to improve write performance. The active delay element 218 may also include additional components, such as leaky diodes or resistors connected in parallel with the switch transistor.
The addition of the active delay element 218 is beneficial because it may add delay to the feedback path through the inverters 202 and 204. The increased feedback delay may give a data state holding transistor of the inverters 202 and 204 time to remove a charge deposited by high energy particles before the feedback is completed. If the data state holding transistor removes the deposited charge before the feedback is completed, the SEU may be avoided. Thus, the addition of the active delay element 218 may improve the SEU hardness of the memory cell 200. Further, the active delay element 218 may not substantially increase the write time of the memory cell 200 during dynamic mode.
However, there may also be disadvantages to the addition of the active delay element 218 to the memory cell 200. One disadvantage is that capacitive coupling generated in the active delay element 218 may disturb write data that passes through the active delay element 218 during a write operation. The capacitive coupling may be generated in the switch transistor of the active delay element 218, or may be generated in the leaky diode of the active delay element 218. If the capacitive coupling of the active delay element 218 sufficiently alters the voltage potential of the write data at the output of the active delay element 218, the inverter 204 may switch back to its original state, and a write error will occur.
FIG. 3 illustrates how a write error may occur in memory cell 200 when the active delay element 218 includes a NMOSFET switch transistor with its gate connected to the non-inverted word line WL. FIG. 3 depicts the voltage potential during a write operation for the bit line BL, the word line WL, the input of the active delay element 218 (BIT), the output of the active delay element 218 (BITISO), and the output of the inverter 204 (NBIT). Typically, a “1” may be written in the memory cell 200 that is holding a “0” by raising both the non-inverted bit line BL and the word line WL to a “1” and pulling the inverted bit line NBL to a “0.”
A “write 1” operation is initialized in FIG. 3 at time t0. As shown in the Figure, BIT is set to “1” and NBIT is set to “0” at time t0. The “1” at BIT is then passed through the active delay element 218, causing BITISO to transition from “0” to a degraded “1” between time t0 and time t1. However, the capacitive coupling in the active delay element 218 may disturb the voltage potential of BITISO at time t1, when the non-inverted word line WL transitions from “1” back to “0.” As shown in the Figure, the capacitive coupling in the active delay element 218 may drop the voltage potential of BITISO below the switch point of the inverter 204. Accordingly, when the write operation is complete at time t1, NBIT will switch back to “1,” BIT will be driven back to “0,” and a “1” will not be written to memory cell 200.
A similar problem may occur when the active delay element 218 includes a PMOSFET switch transistor with its gate connected to an inverted word line, and a “write 0” operation is initialized. Further, as SRAM cells become more scalable and the source VDD decreases, write errors may become more prevalent as a result of smaller write margins. Accordingly, there is a need for a SRAM cell that prevents write errors caused by capacitive coupling in an active delay element.